The present invention relates to a semiconductor device and in particular relates to a semiconductor device which enables a high speed operation.
Examples of semiconductor devices which enable a high speed operation are memory devices such as a SRAM and a DRAM or arithmetic units such as a microcomputer and a microprocessor.
The semiconductor device has several internal circuits such that in order to enable a high speed operation thereof, the respective internal circuits are required to be operable at high speed.
Examples of the internal circuits are input buffer circuits, decoder circuits, memory cells, sense amplifiers, signal change (or transition) detection circuits (or ATD circuits), amplifiers, output buffer circuits and the like.
Generally, an input buffer circuit which generates two output signals that are mutually in a complementary relation to one input signal is constituted of an input level converter circuit section and a driver circuit section which responds to the output of the input level converter circuit section. Further, the driver circuit section is constituted of a non-reversing buffer circuit which outputs a non-reversing signal corresponding to the output of the input level converter circuit section, and a reversing buffer circuit parallel thereto which outputs a reversing signal.
FIG. 1 shows such an input buffer circuit where the output of an inverter 201, to which an input signal Ai is applied, is transformed to an output signal ai through inverters 202 and 203, and is also transformed to an output signal ai through an inverter 204.
In such an input buffer circuit, in the case where the input signal Ai is "Low" level, the output signal ai becomes "Low" level and the output signal ai becomes `High` level.
However, as shown in FIG. 1, the driver circuit that outputs the output signal ai is constructed by connecting two inverters 202 and 203 in cascade, and includes one more inverter stage than a driver circuit that outputs the output signal ai.
Therefore, the delay time incurred for effecting an input signal to output signal transfer, such as with respect to achieving the output signal ai, is greater by the gate delay of one additional inverter stage than that of the output signal ai. Therefore, when considering a buffer circuit built into a memory system, if there is a delay time difference between the inverted signal and non-inverted signal, the decoder circuit connected in a later stage of the input buffer circuit operates by the late signal, which becomes a great hindrance to a high-speed input buffer circuit. Also, the delay time difference, may generate a hazard in the decoder circuit and become an adverse effect on the circuit operation.
Also, as in conventional ones, the level converter part of an input buffer circuit that uses only CMOS inverters is provided in two stages in which there is one more stage than that in the case shown in FIG. 1. This is because the logical threshold voltage V.sub.VTH of the first stage CMOS inverter in the level converter part must be set to the mean amplitude of the input signal (in normal operation, `Low`: 0 [V], `High`: 3 [V]). In other words, by determining the gate width or gate length of the PMOS and NMOS transistors of the CMOS inverter to obtain such a V.sub.LTH, the output signal of the CMOS inverter becomes excessively faster in the case where it changes from `High` to `Low` than in the case where it changes from `Low` to `High`. This difference associated with the switching speed can be a cause of the hazard in the decoder circuit. Because of this, normally, the level converter circuit, in order to eliminate the difference in the time changing from `Low` to `High` and the time changing from `High` to `Low`, adds one more inverter circuit to thereby effect a two stage construction.
Therefore, there has also been expectations for a high-speed level inverter part.
Further, the decoder circuit is formerly known as one constituted of logical gates in three stages or four stages. (Japanese Patent Laid-Open No. 60-170090 (1985))
FIG. 2 is a block diagram of an example of a prior decoder circuit. According to this diagram, the f.0 and the numerical value mentioned in each gate, is the fan-out number of the corresponding gate.
However, when a decoder circuit is composed with three stage or four stage logical gates as above, a great amount of time for the signal transmission from the input to the output is needed. As a result, a high speed operation of the semiconductor memory apparatus, when viewed as a whole, is hindered. (For example, in the construction of FIG. 2, a delay time of about 2.4 nsec is needed from the primary stage input to the final output.)
Therefore, various measures for the stage reductions of the logical gates were tried, but by reducing the stages, the fan-out for each gate increases, and as a result, the load capacity for each gate becomes greater. Such an increase in the load capacity presents a problem of causing the increase of the delay time instead.
A further conventional device is illustrated in FIG. 3.
The same drawing illustrates a part of the circuit of the device, including the connection from a memory cell to a sense amplifier, in the example disclosed in Japanese Patent Application Laid-Open No. 60-132416 (1985).
In the following explanation, a bipolar transistor is called a transistor and a MOSFET a MOS.
Symbols B1 and B2 respectively show an example of a data line block in a memory cell array. Among a plurality of memory cell array arranged in matrix into X direction and Y direction, by inputting signals, for example, to a signal line X1 and signal lines Y1, Y2, . . . , memory cells to be accessed are selected.
Symbols DL1.about.DL4 represent data lines, symbols CELL1 and CELL2 represent memory cells each of which has a latch function, symbols M5, M6, M7 and M8 represent transfer MOS which decide whether memory cell information is to be transferred to data lines corresponding thereto, and symbols M9.about.M12 represent transfer MOS which decides whether data line information corresponding thereto is to be transferred to common data lines CD1, and CD2.
B3 is a presensing block which converts a differential voltage input signal from the common data lines into a differential current signal. Symbols Q1 and Q2, each is a transistor for level shifting, symbols D1 and D2, each is a diode, symbols M13 and M15, each is a MOS. In this presensing block, such operation is effected that through transistors Q3 and Q4 and MOS M14, constituting a differential amplifier, the differential voltage inputted to the bases of Q3 and Q4 is converted into a current signal and is transferred to common collector lines CC1 and CC2.
Usually a plurality of presensing blocks B4 similar to B3 are connected to the same pair of common collector lines, selection of a signal among these is carried out by selecting signals inputted to terminals S1, S2, . . .
A block B5 is a circuit which converts a current signal inputted from the common collector lines CC1 and CC2 into a voltage signal and outputs the same to terminals O1 and O2. Resistor elements R1 and R2, transistors Q7 and Q8, a diode D3 and MOSs M19.about.M21 constitute a cascode amplifier, and the differential current input from CC1 and CC2 is outputted between collectors of Q7 and Q8 as differential voltage. Transistors Q10 and Q11, diodes D4 and D5 and MOSs M22 and M23 constitute a level shifting circuit, and convert into a signal level suitable for the input to a next stage differential amplifier composed of resistor elements R3 and R4, transistors Q12 and Q13 and MOS M24.
In general, for transmitting an electrical signal at high speed, it is important to lower signal amplitude in a signal passage and reduce both the parasitic capacitance and the parasitic resistance in this passage. For example, in the conventional circuit of FIG. 3, when memory capacity is required to be increased, the capacitance and resistance of the above common data lines and common collector lines inevitably become large, so that concurrent realization of both memory capacity increase and high speed operation of the memory device become difficult.
Further, in a digital memory apparatus which introduces the so-called inner synchronizing method, the change in the address signal is detected and the reference signal within the LSI is produced. The ATD (Address Transition Detection) circuit is what accomplishes this task.
FIG. 4 shows the construction of the main parts of a prior ATD circuit.
The number of address signal lines increase and decrease according to the memory capacity and its bit construction. The ATD circuit needs to detect the generation of the change of the signal of the address signal line, when any signals change. Therefore, voltage pulse generators 22-1.about.22-n which receive the corresponding outputs of input buffers 21-1.about.21-n and generate, while responding to the changes, voltage pulses 23-1.about.23-n, respectively, are provided to each address signal A.sub.0 .about.An. Each voltage pulse generator circuit 22 is respectively formed of inverters 28-1.about.28-3 and the FETs 29-1.about.29-5, FETs 29-1 and 29-2 carry out the detection of the leading edge, and FETs 29-3 and 29-4 carry out the detection of the trailing edge. This detected output appears at the node of the FET 29-5 as a voltage pulse. The voltage pulse output of each voltage pulse generator circuit 22 is supplied to an OR circuit 24 through the inverter 28-3. The OR circuit 24, by means of FETs 26-1.about.26-n and a FET 27, takes the logical sum of these voltage pulse outputs, and outputs this logical sum signal as a reference signal 25 through an inverter 20.
Further, an example of this type of ATD circuit is indicated in Japanese Patent Laid-Open No. 59-54094 (1984).
In the prior ATD circuit, the transmission of the signals is carried out by the voltage amplitude or the change (High, Low) of the voltage level. Meanwhile, because the drain of each FET 26-1.about.26-n of the OR circuit 24 is in a common connection to the FET, the load of each FET 26 becomes heavy, and because of charge and discharge time requirements of this load, the ability to change the speed, i.e. to increase the speed, of the output voltage of the OR circuit 24 is limited.
Thus, in the prior ATD circuits, there was a limit to a high operating speed, which was a drawback in attempts at reducing the access time of the digital memory apparatus.
Still further, as a prior output buffer circuit of semiconductor apparatuses such as a semiconductor memory and a microprocessor, that handles digital signals, which shortens the access time, and increases the processing speed, Japanese Patent Application Laid-Open No. 59-181828 (1984) is known. This publication features maintaining the output at an intermediate level between "L" level and "H" level preceding the application of the input signal to the output buffer circuit. Also, the scheme disclosed therein reduces noise.
In other words, the principle construction of an output buffer circuit is shown as an equivalent circuit in FIG. 6.
The same figure is assumed to be incorporated within a common LSI chip and contained in a package, and the symbols L1.about.L3 are lead inductances which are added in the case where the LSI is loaded in a package. The multiple number of the output buffer circuits corresponding to the number of outputs, one of which is surrounded by the dotted line, in cases such as a multiple bit construction, are connected in parallel. In the output buffer circuit when the output changes as "L".fwdarw."H".fwdarw."L", the waveforms of the current (I.sub.1) that flows in an output bipolar transistor Q.sub.1 and the current (I.sub.2) that flows in an output NMOS transistor Q.sub.2, and the Vcc voltage (V.sub.A) within the LSI chip and the grounded voltage (G.sub.A), are shown by the solid lines in FIGS. 7(a)-7(d), respectively. As is clear from FIG. 6 and FIGS. 7(a)-7(d), it is required to charge and discharge the load capacitance in raising and lowering the output voltage, respectively; therefore, I.sub.1 and I.sub.2 transiently show a large peak (FIG. 7[b]). At this time, a voltage (V-dI/dt), which is proportional to the time differentiation of the current, is generated at both ends of the lead inductances of L1 and L2. Therefore, the Vcc potential (V.sub.A) within the LSI chip and the grounding potential (G.sub.L) fluctuates transiently (FIGS. 7[c], and 7[d]), which is a similar phenomenon to the generation of noise .DELTA.V on each potential.
Hence, by forming an output voltage as shown by the alternate long and short dashed line in FIG. 7(a) by means of the art stated in Japanese Patent Application Laid-Open No. 59-181828 (1984), the charging and discharging of the load capacitance is divided into two times, and the peak magnitude of the current is lowered (the alternate long and short dashed line of FIG. 7[b]), as a result, reduction of noise caused by L-dI/dt is achieved (the alternate long and short dashed lines of FIGS. 7[c] and [d]).
Further, FIGS. 5(a) through 5(c) are the operating waveforms by the art of the above application, and by applying the transition detector signal (FIG. 5[a]) to the input signal shown in FIG. 5(b), an output signal as shown in FIG. 5(c), which is the same signal shown by the alternate long and short dashed line in FIG. 7(a), is obtained.
However, because the output assumes the mean level of the "L" level and "H" level preceding application of the input signal to the output buffer circuit, there was a problem in that the entire mean level signal becomes an input signal to other semiconductor integrated circuits.
In other words, the other semiconductor integrated circuit concerned, assumes the state to accept only "H" level or "L" level, but because the mean level signal is too close to the threshold voltage (V.sub.th) of the other semiconductor integrated circuit concerned, an adverse influence such as oscillating the input buffer circuit of the other semiconductor integrated circuit occurs.